View PCX107AMZFU100LC_7339331.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

visit our website: www.e2v.com for the latest version of the datasheet e2v semiconductors sas 2007 pc107a pci bridge memory controller datasheet 0842e?hirel?04/07 features processor bus frequency up to 100 mhz 64- or 32-bit data bus and 32-bit address bus provides support for eith er asynchronous sram, burst sram, or pipelined burst sram compliant with pci speci fication, revision 2.1 pci interface operates up to 66 mhz/5.0v compatible ieee ? 1149.1 compliant, jtag boundary-scan interface pd max = 1w (66 mhz), fu ll operating conditions nap, doze and sleep mo des for power savings two-channel integrated dma controller message unit ? intelligent input/output (two-w ire interface) message controller ? two door bell registers ? inbound and outbound messaging registers inter-integrated circuit (two-wire interfa ce) controller, full master/slave support embedded programmable interrupt controller (epic) ? five hardware interrupts (irqs) or 16 serial interrupts ? four programmable timers description the pc107a pci bridge/integrated memory controller provides a bridge between the peripheral component interconnect, (pci) bus and powerpc ? 603e, powerpc 740, powerpc 750 or pc7400 microprocessors. pci support allows system designers to design systems quic kly using peripherals already designed for pci and other stan- dard interfaces available in the personal computer hardware environment. the pc107a provides many other necessities for embedded applications including a high-performance memory controller and dual processor support, 2-channel flexible dma controller, an interr upt controller, an i 2 o-ready message unit, an inter-integrated circuit controller ( two-wire interface ), and low skew clock drivers. the pc107a contains an embedded pr ogrammable interrupt controller (epic) featuring five hardware interrupts (irq?s) as well as sixteen serial interrupts along with four timers. the pc107a uses an advanced, 2.5v hip3 process technology and is fully compatible with ttl devices.
2 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 screening this product is manufactur ed in full compliance with: hitce cbga according to e2v standards pbga upscreening based upon e2v standards full military temperature ra nge (tj = -55c, +125c) industrial temperature range (tj = -40c, +110c) 1. general description 1.1 simplified block diagram the pc107a integrates a pci bridge, memory controller, dma controller, epic interrupt controller/tim- ers, a message unit with an intelligent input/output (i 2 o) message controller, and an inter-integrated circuit (two-wire interface) controller. the integr ation reduces the overall packaging requirements and the number of discrete devices required for an embedded system. figure 1-1 shows the major functional units within the pc107a. note that this is a conceptual block dia- gram intended to show the basic features rather than an attempt to show how these features are physically implemented. figure 1-1. pc107a block diagram data (64-bit) 60x bus interface (64- or 32-bit data bus) address (32-bit) dll pll fanout buffers additional features: programmable i/o with watchpoint jtag/cop interface power management sdram_sync_in sdram clocks cpu clocks pci_sync_in pci bus clocks memory/rom/ port x control/ address data bus (64- or 32-bit) with 8-bit parity or ecc osc_in five request/grant pairs 32-bit pci interface i2c 5 irqs/ 16 serial interrupts epic interrupt controller /timers address translator pci arbiter pc107 i2c controller dma controller message unit (with i2o) peripheral logic block central control unit data path ecc controller memory controller configuration registers pci bus interface unit
3 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 1.1.1 general parameters the following list provides a summary of the general parameters of the pc107a: technology 0.29 m cmos, five-layer metal die size 50 mm 2 transistor count 0.96 million logic design fully-static package surface mount 503 plas tic ball grid array (c4/pbga) core power supply 2.5 5% v dc (nominal; see table 5-2 on page 12 for recommended operating conditions) i/o power supply 3.0 to 3.6v dc 1.2 features the pc107a provides an integrated high-bandwidth, high-performance interface between up to two 60x processors, the pci bus, and main memory. this sect ion summarizes the features of the pc107a. major features of the pc107a are as follows: memory interface ? 64-/32-bit 100 mhz bus ? programmable timing supporting either fpm dram, edo dram or sdram ? high-bandwidth bus (32-/64-bit data bus) to dram ? supports one to eight banks of 4-, 16-, 64-, or 128-mbit memory devices, and up to four banks of 256 mbit sdram devices ? supports 1m byte to 1 gbyte dram memory ? 144m bytes of rom space ? 8-, 32-, or 64-bit rom ? write buffering for pci and processor accesses ? supports normal parity, read-modify-write (rmw), or ecc ? data-path buffering between memory interface and processor ? low-voltage ttl logic (lvttl) interfaces ? port x: 8-, 32-, or 64-bit general-purpose i/o port using rom controller interface with programmable address strobe timing 32-bit pci interface operating up to 66 mhz ? pci 2.1-compliant ? pci 5.0v tolerance ? support for pci locked accesses to memory ? support for accesses to pci memory, i/o, and configuration spaces ? selectable big- or little-endian operation ? store gathering of processor-to-pci write and pci-to-memory write accesses ? memory prefetching of pci read accesses ? selectable hardware-enforced coherency ? pci bus arbitration unit (five request/grant pairs)
4 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 ? pci agent mo de capability ? address translation unit ? some internal configuration registers accessible from pci two-channel integrated dma controller (writes to rom/port not supported) ? supports direct mode or chaining mode (automatic linking of dma transfers) ? supports scatter gathering-read or write discontinuous memory ? interrupt on completed segment, chain, and error ? local-to-local memory ? pci-to-pci memory ? pci-to-local memory ? pci memory-to-local memory message unit ? two doorbell registers ? an extended doorbell register mechanism that facilitates interprocessor communication through interrupts in a dual-local-processor system ? two inbound and two outbound messaging registers ?i 2 o message controller two-wire interface controller with full master/slave support (except broadcast all) embedded programmable interrupt controller (epic) ? five hardware interrupts (irqs) or 16 serial interrupts ? four programmable timers integrated pci bus, cpu, and sdram clock generation programmable pci bus, 60x, and memory interface output drivers dynamic power management ? supports 60x nap, doze, and sleep modes programmable input and output si gnals with watchp oint capability built-in pci bus performance monitor facility debug features ? error injection/capture on data path ? ieee 1149.1 (jtag)/test interface processor interface ? supports up to two powerpc microprocessors with 60x bus interface ? supports various operating frequencies and bus divider ratios ? 32-bit address bus, 64/32-bit data bus supported at 100 mhz ? supports full memory coherency ? supports optional local bus slave ? decoupled address and data buses for pipelining of 60x accesses ? store gathering on 60x-to-pci writes ? concurrent transactions on 60x and pci buses supported
5 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 2. pin assignments 2.1 pinout listings table 2-1 provides the pinout listing for the pc107a, 503 pbga package. table 2-1. pc107a pinout listing signal name package pin number pin type supply voltage output driver type notes 60x processor interface signals a[0?31] ae22, ae16, aa14, ae17, ad21, ad14, ad20, ab16, ab20, ab15, aa20, ad13, y15, ae12, ad15, ab9, ab14, aa8, ac13, y12, y11, ae15, ae13, aa16, y13, ab8, ad12, ae10, ab13, y9, y8, ad9 i/o bv dd drv_cpu (4) aack ac7 output bv dd drv_cpu artry y7 i/o bv dd drv_cpu (15) bg0 ae11 output bv dd drv_cpu bg1 ad11 output bv dd drv_cpu br0 ab17 input bv dd ? br1 y14 input bv dd ? (10) ci ad16 i/o bv dd drv_cpu dbg0 ac10 output bv dd drv_mem_addr dbg1 ad10 output bv dd drv_mem_addr dbglb ab10 output bv dd drv_mem_addr dh[0?31] p1, r1, p2, t4, t1, t3, r4, p6, u6, v5, v2, t5, u1, r6, w1, v4, w2, u4, t2, v6, w3, w5, y1, y2, y4, y5, aa1, aa2, aa4, ab1, ab3, ab4 i/o bv dd drv_cpu (4) dl[0?31] aa7, w6, ab6, aa6, ab5, ac4, ad3, ab7, ae1, w4, n6, m1, n3, n4, n5, n1, m2, r2, v1, p5 , p4, n2, u2, ae4, ae6, ae2, ae3, ae7, ad5, ab2, ac2, ac1 i/o bv dd drv_cpu (4) dp[0?7] ae9, ad6, ad8, ad1, ae8, ad7, ad4, ae5 i/o bv dd drv_cpu (4) gbl ad17 i/o bv dd drv_cpu lbclaim y17 input bv dd ta ae14 i/o bv dd drv_cpu (15) tbst ae21 i/o bv dd drv_cpu tea ab11 output bv dd drv_cpu ts aa10 i/o bv dd drv_cpu (15) tsiz[0?2] ae19, ad18, ab18 i/o bv dd drv_cpu (4)
6 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 tt[0?4] ad19, ac19, ab19, aa19, aa18 i/o bv dd drv_cpu (4) wt ac16 i/o bv dd drv_cpu pci interface signals ad[31?0] n23, n21, m20, m21, m22, m24, m25, l20, l22, k25, k24, k23, k21, j20, j24, j25, h20, f24, e25, f21, e24, e22, d25, a25, b25, a23, b23, b22, c22, c25, d23, d21 i/o ov dd drv_pci (4)(11) c/be [3?0] l24, j22, g22, a24, i/o ov dd drv_pci (4)(11) devsel g23 i/o ov dd drv_pci (6)(11) frame g20 i/o ov dd drv_pci (6)(11) gnt [4?0] t24, p22, p21, r22, n20 output ov dd drv_pci (4)(11) idsel l25 input ov dd ? inta v21 output ov dd drv_pci (6)(11)(12) irdy h24 i/o ov dd drv_pci (6)(11) lock g21 input ov dd ? (6) par g24 i/o ov dd drv_pci (11) perr g25 i/o ov dd drv_pci (6)(11)(13) req [4?0] w25, v25, u25, t25, t23 input ov dd ? (10) serr f25 i/o ov dd drv_pci (6)(11)(12) stop h21 i/o ov dd drv_pci (6)(11) trdy h25 i/o ov dd drv_pci (6)(11) memory interface signals as a4 output gv dd drv_mem_addr cas /dqm[0?7] a2, b1, a11, a10, b3, c2, f12, d11 output gv dd drv_mem_addr (4) cke a12 output gv dd drv_mem_addr (1) foe a13 i/o gv dd drv_mem_addr (1)(2) mdh[0?31] m6, l4, l6, k2, k4, k5, j4, j6, h4, h5, g3, g5, g6, f5, f1, e1, b14, d15, b15, e16, d16, c16, d18, d17, b17, f18, e19, e20, b19, b20, b21, a22 i/o gv dd drv_mem_data (4) mdl[0?31] m5, l1, l2, k1, k3, j1, j2, h1, h2, h6, g2, g4, f4, g1, f2, e2, f14, f15, a16, f17, b16, a17, a18, a19, b18, e18, d19, f19, a20, c19, d20, a21 i/o gv dd drv_mem_data (3)(4) par/ar[0?7] d2, c1, a15, a1 4, d1, d3, f13, c13 i/o gv dd drv_mem_data (4) ras /cs [0?7] e6, c4, d5, e4, c10, f11, b10, b11 output gv dd drv_mem_addr (4) rcs0 d10 i/o gv dd drv_mem_addr (1)(2) table 2-1. pc107a pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
7 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a rcs1 b9 output gv dd drv_mem_data rcs2 b5 output gv dd drv_mem_addr rcs3 d7 output gv dd drv_mem_addr sdba0 a9 output gv dd drv_mem_addr (1)(2) sdba1 a8 output gv dd drv_mem_addr sdcas d4 output gv dd drv_mem_addr (1) sdma[13?0] e10, f9, d9, f8, e8, d8, b8, e7, c7, b7, a7, b6, a6, a5 output gv dd drv_mem_addr (4)(5) sdras b4 output gv dd drv_mem_addr (1) we a3 output gv dd drv_mem_addr epic control signals int y22 output ov dd drv_cpu (16) irq_0 / s_int u24 input ov dd ? irq_1 / s_clk c24 i/o ov dd drv_pci irq_2 / s_rst t21 i/o ov dd drv_pci irq_3 / s_frame u20 i/o ov dd drv_pci irq_4/ l_int v22 i/o ov dd drv_pci two-wire interface control signals scl ab25 i/o ov dd drv_cpu (8)(12) sda ab24 i/o ov dd drv_cpu (8)(12) clock signals cko v20 output ov dd drv_pci cpu_clk[0?2] aa12, aa13, ab12 output bv dd drv_mem_addr (4) osc_in u22 input ov dd ? pci_clk[0?4] r25, p24, r24, n24, n25 output ov dd drv_mem_addr (4) pci_sync_in p20 input ov dd ? pci_sync_out p25 output ov dd drv_mem_addr sdram_clk[0?3] d14, d13, e12, e14 output gv dd drv_mem_addr (4) sdram_sync_in e13 input gv dd ? sdram_sync_out d12 output gv dd drv_mem_addr miscellaneous signals hreset aa23 input ov dd ? hreset_cpu ab21 output bv dd drv_cpu (10)(12) mcp ae20 output ov dd drv_cpu (12)(16) nmi ac25 input ov dd ? table 2-1. pc107a pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
8 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 qack ae18 output bv dd drv_cpu (10) qreq m4 input bv dd ? sreset y18 output bv dd drv_cpu (10) test/configuration signals pll_cfg[0?3] ac22, ad23, ad22, ae23 input ov dd ? (2)(4) tck w24 input ov dd ? (7)(10) tdi y25 input ov dd ? (7)(10) tdo w23 output ov dd drv_pci test aa25 input ov dd ? (7)(10) test1 v24 input ov dd ? (8) test2 d6 input gv dd ? (9) tms y24 input ov dd ? (7)(10) trig_in w22 input ov dd ? trig_out w21 output ov dd drv_cpu (10) trst aa24 input ov dd ? (7)(10)(14) power and ground signals av dd ae24 input ? ? gnd aa21, ab22, ac11, ac14, ac17, ac20, ac23, ac3, ac5, ac8, ad24, ae25, c12, c15, c18, c21, c23, c3, c6, c9, e3, f10, f16, f20, f23, f6, g11, g13, g15, g 18, g8, h19, h3, h7, j23, k20, k6, l19, l3, l7, m23, n19, n7, p3, r19, r23, r7, t20, t6, u3, v19, v23, v7, w11, w13, w15, w18, w8, y10, y16, y19, y20, y3, y6 input ? ? gv dd b2, c5, c8, c11, c14, c17, c20, e5, e9, e11, e15, e17, f3, g7, g9, g12, g14, g17, g19, j3, j5, j7, l5, m3, m7 input ? ? lav dd f7 input ? ? lv dd d22, f22, h22, k22, n22, t22 input ? ? ov dd b24, e21, e23, h23, j19, j21, l21, l23, m19, p19, p23, r21, u19, u21, u23, y23 input ? ? bv dd p7, r3, r5, u5, u7, v3, w7, w9, w12, w14, w17, aa3, aa5, aa9, aa11, aa15, aa17, ac6, ac9, ac12, ac15, ac18, ac21, ad2 input ? ? v dd k19, w16, t19, g10, g16, k7, t7, w10, w19, w20, y21, aa22, ab23, ac24, ad25 input ? ? table 2-1. pc107a pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
9 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a notes: 1. this pin has an internal pull-up resistor which is enabled only when the pc107a is in the reset state. the value of the inter- nal pull-up resistor is not guaranteed, but is sufficient to ensu re that a logic "1" is read into configuration bits during res et. 2. this pin is a reset configuration pin. 3. mdl[0] is a reset configuration pin and has an internal pull-up resistor which is enabled only when the pc107 is in the reset state.the value of the internal pull-up resist or is not guaranteed, but is sufficient to insure that a logic '1' is read into c onfigu- ration bits during reset. 4. multi-pin signals such as ad[0?31] or dl[0?31] have their ph ysical package pin numbers listed in order corresponding to the signal names. ex: ad0 is on pin d21, ad1 is on pin d23,... ad31 is on pin n23. 5. sdma[10?1] are reset configuration pins and have internal pull-up resistors which are enabled only when the pc107 is in the reset state.the values of the internal pull-up resistors is not guaranteed, but are sufficient to ensure that logic "1"s ar e read into the configuration bits during reset. 6. recommend a weak pull-up resistor (2 k ? ? 10 k ? ) be placed on this pci control pin to lv dd . 7. v ih and v il for these signals are the same as the pci v ih and v il entries in table 7-1 , ?dc electrical specifications.? 8. recommend a weak pull-up resistor (2 k ? ? 10 k ? ) be placed on this pin to ov dd . 9. recommend a weak pull-up resistor (2 k ? ? 10 k ? ) be placed on this pin to gv dd . 10. this pin has an internal pull-up resistor; the value of the inte rnal pull-up resistor is not guaranteed, but is sufficient t o prevent unused inputs from floating. 11. this pin is affected by programmable pci_hold_del parameter, see ?pci signal output hold timing? on page 28 .? 12. this pin is an open drain signal. 13. this pin is a sustained tri-state pin as defined by the pci local bus specification. 14. see ?connection recommendations? on page 42 for additional information on this pin. 15. a weak pull-up resistor is recommend (2 k ? ? 10 k ? ) to be placed on this pin to bv dd . 16. if bv dd = 2.5v 5%, this microprocessor interface pin needs to be dc voltage level shifted from ov dd (3.3 0.3v) to 2.5v 5%; this can typically be accomplished with a two resistor voltage divider circuit since the signal is an output only signal. manufacturing pins ftp[2?3] r20, d24 i/o ov dd drv_pci (4)(8) mtp[1?2] b12, b13 i/o gv dd drv_mem_addr (4)(9) table 2-1. pc107a pinout listing (continued) signal name package pin number pin type supply voltage output driver type notes
10 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 3. signal description figure 3-1. pc107a microprocessor signal groups 32 a[0-31] 1 aack 1 artry 1 bg0 1 bg1 1 br0 1 br1 1 ci 1 dbg0 1 dbg1 1 dbglb 32 dll[0-31] 60x processor interface signals 32 dl[0-31] 1 gbl 1 lbclaim 1 ta 1 tbst 1 tea 1 ts 3 tsiz[0-2] 5 tt[0-4] 1 wt 32 ad[0-31] 4 c/be[0-3] 1 devsel 1 frame 5 gnt[0-4] 1 idsel 1 inta 1 irdy 1 par 1 perr 6 req[0-4] 1 serr pci interface signals 1 stop 1 trdy 1 lock 1 8 1 1 32 32 8 8 1 1 1 1 1 1 1 1 1 14 memory interface signals cas/dqm[0-7] cke foe we sdras sdma[13-0] sdcas sdba1 sdba0 mdh[0-31] mdl[0-31] par/ar[0-7] ras/cs[0-7] rcs0 rcs1 rcs2 rcs3 1 1 1 1 1 1 1 epic control signals int irq_0/s_int irq_1/s_clk irq2_2/s_rst irq_3/s_frame irq_4/l_int 1 1 scl sda two-wire interface control signals cpuclk[0-2] cko 1 3 osc_in 1 pci_clk[0-4] 5 clock signals pci_sync_in 1 pci_sync_out 1 4 sdram_clk[0-3] sdram_sync_in 1 sdram_sync_out 1 1 1 1 1 1 1 1 hreset hreset_cpu mcp nmi qack qreq sreset test/configuration signals 4 1 1 1 1 1 1 1 1 1 1 pll_cfg[0-3] tck tdi tdo test test1 test2 tms trig_in trig_out trst 1 64 avdd gnd 25 gvdd 1 6 lavdd lvdd 16 ovdd 24 bvdd 15 vdd ftp[2-3] 2 mtp[1-2] 2 miscellaneous signals power and ground signals manufacturing pins 8 dl[0-7] as
11 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 4. detailed specification this specification describes the s pecific requirements for the pc107a, in compliance with e2v standard screening. 5. applicable documents 1. mil-std-883: test methods and procedures for electronics. 2. sq32s0100.0: quality levels for supplied components. the microcircuits are in accordance with the applicable documents and as specified herein. 5.1 design and construction 5.1.1 terminal connections the terminal connections are shown in table 2-1 on page 5 . 5.2 absolute maximum ratings the tables in this section describe the pc107a dc electrical characteristics. table 5-1 provides the absolute maximum ratings. notes: 1. functional and tested operating conditions are given in table 5-2 . absolute maximum ratings are stress ratings only and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or ca use permanent damage to the device. 2. pci inputs with lv dd = 5v 5% v dc may be correspondingly stressed at voltages exceeding lv dd + 0.5v dc. table 5-1. absolute maximum ratings symbol characteristic (1) value unit v dd supply voltage ? core -0.3 to 2.75 v gv dd supply voltage ? memory bus drivers -0.3 to 3.6 v bv dd supply voltage ? processor bus drivers -0.3 to 3.6 v ov dd supply voltage ? pci and standa rd i/o buffers -0.3 to 3.6 v av dd /lav dd supply voltage ? plls and dll -0.3 to 2.75 v lv dd supply voltage ? pci reference -0.3 to 5.4 v v in input voltage (2) -0.3 to 3.6 v t j operational die-junction temperature range -55 to 125 c t stg storage temperature range -65 to 150 c
12 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 5.3 recommended o perating conditions table 5-2 provides the recommended operating conditions for the pc107a. notes: 1. pci pins are designed to withstand lv dd + 0.5v dc when lv dd is connected to a 5.0v dc power supply. 2. pci pins are designed to withstand lv dd + 0.5v dc when lv dd is connected to a 3.3v dc power supply. cautions: 3. input voltage (v in ) must not be greater than the supply voltage (v dd /av dd /lav dd ) by more than 2.5v at all times, including during power-on reset. 4. ov dd must not exceed v dd /av dd /lav dd by more than 1.8v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 5. v dd /av dd /lav dd must not exceed ov dd by more than 0.6v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 6. bv dd /gv dd must not exceed v dd /av dd /lav dd by more than 1.8v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. 7. lv dd must not exceed v dd /av dd /lav dd by more than 5.4v at any time including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences 8. lv dd must not exceed ov dd by more than 3.6v at any time, including during power-on reset. this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down sequences. table 5-2. recommended operating conditions symbol characteristic recommended value unit notes v dd supply voltage 2.5 5% v (4) gv dd supply voltages for memory bus drivers 3.3 5% v (6) bv dd supply voltages for processor bus drivers 3.3 5% v (6) 2.5 5% ov dd i/o buffer supply for pci and standard 3.3 0.3 v (4) av dd pll supply voltage 2.5 5% v (5) lav dd dll supply voltage 2.5 5% v (5) lv dd pci reference 5.0 5% v (7)(8) 3.3 0.3 v (7)(8) v in input voltage pci inputs 0 to 3.6 or 5.75 v (1)(2) all other inputs 0 to 3.6 v (3) t j die-junction temperature -55c to 125c c
13 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a figure 5-1 shows the supply voltage sequencing and separation cautions. figure 5-1. supply voltage sequencing and separation cautions notes: 1. numbers associated with waveform separ ations correspond to caution numbers listed in table 5-2, ?recommended operating conditions,? on page 12 . 2. refer to ?power supply voltage sequencing? on page 41 for additional information. 3. refer to table 7-4 on page 24 for additional information on pll relock and reset signal assertion timing requirements. 4. refer to table 7-5 on page 25 for additional information on reset configuration pin setup timing requirements. 5. hreset must transition from a logic 0 to a logic 1 in less than one sdram_sync_in clock cycle for the device to be in the non-reset state. 6. hreset_cpu negates 2 17 memory clock cycles after hreset negates. ovdd/bvdd/gvdd(lvdd at 3.3v ----) vdd/avdd/lavdd lvdd at 5v time 3.3v 5v 2.5v 0 6 9 8 8 9 5.7 dc power supply voltage voltage regulator delay (2) reset configuration pins hreset asserted 255 external memory clock cycles (3) 9 external memory clock cycles setup time (4) hreset_cpu hreset vdd stable see note 1 below. vm = 1.4v vm = 1.4v maximum rise time must be less than one external memory clock cycle (5) 100 s pll relock time (3) power supply ramp up (2) 6
14 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 figure 5-2 shows the undershoot and overshoot voltage of the memory interface of the pc107a. figure 5-2. overshoot/undershoot voltage figure 5-3 and figure 5-4 show the undershoot/overshoot voltage of the pci interface for 3.3 and 5v sig- nals, respectively. figure 5-3. maximum ac waveforms for 3.3v signaling gnd gnd - 0.3v gnd - 1.0v not to exceed 10% gvdd of tsdram_clk 4v vih vil gvdd +5% +3.6v 0v 11 ns (min) +7.1v 4 ns (max) 4 ns (max) -3.5v overvoltage waveform undervoltage waveform 62.5 ns 7.1v p-to-p (min) 7.1v p-to-p (min)
15 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a figure 5-4. maximum ac waveforms for 3.3v signaling 6. thermal information 6.1 package characteristics table 6-1 provides the package thermal characteristics for the pc107a. note: 1. junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temp erature, airflow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single-layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed-circuit board per jedec jesd51-8. board temper- ature is measured on the top surf ace of the board near the package. 5. thermal resistance between the die and the case top surface without thermal grease. ? 0v 7.1v p-to-p (min) 7.1v p-to-p (min) +3.6v 11 ns (min) +7.1v 4 ns (max) 4 ns (max) -3.5v overvoltage waveform undervoltage waveform 62.5 ns table 6-1. fc-pbga package thermal characteristics symbol characteristic (1) value unit r ja junction-to-ambient natural convection (1)(2) (single-layer board-1s) 30 c/w r jma junction-to-ambient natural convection (1)(3) (four-layer board-2s2p) 26 c/w r jma junction-to-ambient (at 200 ft/min) (1)(3) (single-layer board-1s) 25 c/w r jma junction-to-ambient (at 200 ft/min) (1)(3) (four-layer board-2s2p) 22 c/w r jb junction-to-board (4) 20 c/w r jc junction-to-case (5) < 0.1 c/w
16 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 6.1.1 package thermal characteristics for hitce table 6-2 provides the package thermal characteristics for the pc107 hitce. notes: 1. nominal values: means computed with nominal geometry and nominal thermal conductivities of materials as given in legend of each simulation results. 2. in this case thermal resistance junction to case is thermal resistance junction to top of silicon die, and value almost not depend from substrate used for land grid array. value depends stro ngly on heating zone size in silicon chip assumption. in present simulations heating zone is 5.8 mm 3.65 mm that is 42% of die size. assuming the full die size as uniformly power dissipating is not realistic. assuming 8.3 mm 5.15 mm heating zone (85% of die su rface) leads to 0.15c/watt instead of 0.29c/watt. 6.1.2 thermal management information an estimation of the chip junction temperature, t j , can be obtained from the equation: t j = t a + (r ja p d ) where t a = ambient temperature for the package (c) r ja = junction-to-ambient thermal resistance (c/w) p d = power dissipation in the package (w) the junction-to-ambient thermal resistance is an in dustry-standard value that provides a quick and easy estimation of thermal performance. table 6-1 has four junction-to-ambient thermal resistances (r ja or r jma ). two test boards are used: single-signal-layer (1 s) and four-layer boards with two internal planes (2s2p). which value is closer to the application depe nds on the system board thermal resistance and the density of other high-power dissipation components. to illustrate the process, determine the junction temperature based on the values provided in table 6-1 for an pc107 that is mounted on a board with many internal planes using arbitrary values. if the pc107 is doing most of the power dissipation, use r jma of 26c/w given in table 6-1 . the ambient tempera- ture near the device is 45c. suppose the total typical power dissipation at 100 mhz core frequency is 2.1w (see table 6-3 ). the junction temperature is: t j = 45 + (2.1 26) = 100c. if this value is less than the maximum junction temperature noted in table 5-1 , the pc107 will not need a heat sink. if the ambient temperature is higher or the power dissipation is higher because of faster bus speed, the device will prob ably need a heat sink. table 6-2. package thermal characte ristics for hitce package (1) characteristic value unit pc107 hitce thermal resistance junction to case (2) 0.295 c/watt thermal resistance junction to bottom of balls 15.8 c/watt thermal resistance junction to board, jedec jesd51-8 (2s2p board) 18.4 c/watt thermal resistance junction to ambient, jedec jesd51-2 (2s2p board = 2 signals + 2 power planes in board) 26.3 c/wat t
17 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a the pc107 may need a heat sink depending on the system. this section provides thermal management information for the flip chip plastic ball grid array (fc-pbga) package for air-cooled applications. proper thermal control design is primarily dependent on the sy stem-level design?the heat sink, airflow, and ther- mal interface material. to reduce the die-junction temperature, heat sinks may be attached to the package by several methods?spring clip to holes in the printed-circuit board or package, and mounting clip and screw assembly (see figure 6-1 ); however, due to the potential large mass of the heat sink, attachment through the printed-circuit board is suggested. the force of the heat sink on the die should not exceed 6 lb. the heat sink surface must be flat without protrusion s and must be parallel with the die as the heat sink is brought into contact to avoid chipping the edges of the die and the heat sink. because of the small contact area of the heat sink, it is suggested that the mounting force be centered over the die. figure 6-1. package exploded cross-sectional view with several heat sink options the board designer can choose between several types of heat sinks to place on the pc107. there are several commercially available heat sinks for the pc107 provided by the listvendors: aavid thermalloy 603-224-9988 80 commercial st. concord, nh 03301 internet: www.aavidthermalloy.com alpha novatech 408-749-7601 473 sapena ct. #15 santa clara, ca 95054 internet: www.alphanovatech.com international electronic research corporation (ierc) 818-842-7277 413 north moss st. burbank, ca 91502 internet: www.ctscorp.com fc-pbga package thermal interface material heat sink heat sink clip printed-circuit board
18 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 tyco ? electronics 800-522-6752 chip coolers p.o. box 3668 harrisburg, pa 17105-3668 internet: www.chipcoolers.com wakefield engineering ? 603-635-5102 33 bridge st. pelham, nh 03076 internet: www.wakefield.com ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal per- formance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. 6.1.3 internal package conduction resistance for the pbga packaging technology, the intrinsic conduction thermal resistance paths are as follows: the die junction-to-case thermal resistance, the die junction-to-ball thermal resistance. figure 6-2 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. figure 6-2. c4 package with heat sink mounted to a printed-circuit board note: the internal versus external package resistance for this pbga package, heat is dissipated from the component via several concurrent paths. heat is conducted through the silicon and may be removed to the am bient air by convection and/or radiation. in addition, a second, parallel heat flow path exists by conduction in parallel through the c4 bumps and the epoxy under-fill, to th e plastic substrate for further convection cooling off the edges. then from the plas- tic substrate, heat is conducted via the leads/balls to the next-level interconnect (printed-circuit board) whereupon the primary mode of heat transfer is by convection and/or radiation. external resistance external re sistance internal resistance radiation convection radiation convection heat sink printed-circuit board thermal interface material package/leads die junction die/package
19 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 6.2 power characteristics table 6-3 provides the preliminary power consumption estimates for the pc107a. power consumption on the pll supply pin (av dd ) and the dll supply pin (lav dd ) < 15 mw. this information is based on characterization data. notes: 1. power is measured with v dd = 2.625v, gv dd = ov dd = bv dd = 3.45v at 0c and one dimm populated in test system. 2. all clock drivers enabled. table 6-3. power consumption mode pci_sync_in/core frequency (mhz) unit notes 25/50 33/33 33/66 66/100 v dd power i/o power v dd power i/o power v dd power i/o power v dd power i/o power typical 468 923 351 759 644 1087 933 1122 mw (1)(2) doze 176 697 118 636 235 800 350 915 mw (1)(2) nap 139 744 93 693 185 420 276 970 mw (1)(2) sleep 79 718 45 677 102 841 138 939 mw (1)(2)
20 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 7. electrical characteristics this section provides the ac and dc electrical specifications and thermal characteristics for the pc107a. 7.1 static characteristics 7.1.1 dc electrical specification table 7-1 provides the dc electrical characteristic s for the pc107a. at recommended operating condi- tions (see table 5-2 on page 12 ) notes: 1. these specifications are for t he default driver strengths indicated in table 7-2 on page 21 . 2. see figure 7-15 on page 34 for pins with internal pull-up resistors. 3. the minimum input high volt age is not compliant with the pci local bus specification (rev 2.1) which specifies 0.5*ov dd for minimum input high voltage. 4. leakage current is measured on input pins and on output pi ns in the high impedance state. the leakage current is mea- sured for nominal ov dd /lv dd and v dd or both ov dd /lv dd and v dd must vary in the same direction. 5. see table 7-2 on page 21 for the typical drive capability of a specific sig nal pin based upon the type of output driver associ- ated with that pi n as listed in table 2-1 on page 5 . 6. capacitance is periodically sampled rather than 100% tested. table 7-1. dc electrical specifications characteristics conditions (1) symbol value unit min max input high voltage (2)(3) pci only v ih 0.65*ov dd (3) lv dd v input low voltage pci only v il ?0.3*ov dd v input high voltage (2) all other pins (gv dd = 3.3v) v ih 2.0 ? v input high voltage (2) all other pins (bv dd = 2.5v) v ih 1.7 ? v input low voltage all inputs except pci_sync_in v il gnd 0.8 v pci_sync_in input high voltage cv ih 2.4 ? v pci_sync_in input low voltage cv il gnd 0.4 v input leakage current for pins using drv_pci driver (4) 0.5v v in 2.7v at lv dd = 4.75 i l ? 70 a input leakage current all others (4) lv dd = 3.6v (gv dd 3.465) i l ? 10 a output high voltage (5) i oh = driver dependent (5) (gv dd = 3.3v) v oh 2.4 ? v output low voltage (5) i ol = driver dependent (5) (gv dd = 3.3v) v ol ?0.4v output high voltage (5) i oh = driver dependent (5) (bv dd = 2.5v) all outputs except cpu_clks[0-2] v oh 1.85 ? v i oh = driver dependent (5) (bv dd = 2.5v) cpuclks[0-2] only v oh 2.0 ? v output low voltage (5) i ol = driver dependent (5) (bv dd = 2.5v) all outputs except cpu_clk[0-2] v ol ?0.4v i ol = driver dependent (5) (bv dd = 2.5v) cpu_clk[0-2] only v ol ?0.3v capacitance (6) v in = 0v, f = 1 mhz c in ?7.0
21 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 7.1.2 output driver characteristics table 7-2 provides information on the characteristics of the output drivers referenced in table 2-1 on page 5 . the values are from the pc107a ibis model (v 1.1) and are not tested, for additional detailed information see the complete ibis model listing at http://www.freescale.com/semiconductor. notes: 1. for drv_pci, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.33v label by interpolating between the 0.3v and 0.4v table entries? current values which corresponds to the pci v oh = 2.97 = 0.9*ov dd (ov dd = 3.3v) where table entry voltage = ov dd - pci v oh . 2. for all others with gv dd or bv dd = 3.3v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.9v table entry which corresponds to the v oh = 2.4v where table entry voltage = g/bv dd - v oh . 3. for all others with bv dd = 2.5v, i oh read from the ibis listing in the pull-up mode, i(min) column, at the 0.65v table entry by interpolating between the 0.6v and 0.7v table ent ries? current values which corresponds to the v oh = 1.85v where table entry voltage = bv dd - v oh . 4. for drv_pci, i ol read from the ibis listing in the pull-do wn mode, i(min) column, at 0.33v = pci v ol = 0.1*ov dd (ov dd = 3.3v) by interpolating between the 0.3v and 0.4v table entries. 5. for all others with gv dd or bv dd = 3.3v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4v table entry. 6. for all others with bv dd = 2.5v, i ol read from the ibis listing in the pull-down mode, i(min) column, at the 0.4v table entry. 7. for bv dd = 2.5v, the i oh and i ol values are estimated from the io_mem_ data_xx_2.5 and io_mem_addr_xx_2.5 sections of the ibis model where xx = driv er output impedance (20 or 40 ? ). table 7-2. drive capability of pc107a output pins driver type programmable output impedance (ohms) supply voltage i oh i ol unit notes drv_cpu 20 bv dd = 3.3v 36.6 18.1 ma (2)(5) bv dd = 2.5v 21.4 15.6 ma (3)(6)(7) 40 (default) bv dd = 3.3v 18.6 9.2 ma (2)(5) bv dd = 2.5v 10.8 7.9 ma (3)(6)(7) drv_pci 25 ov dd = 3.3v 12.0 12.4 ma (1)(4) 50 (default) ov dd = 3.3v 6.1 6.3 ma (1)(4) drv_mem_addr drv_pci_clk 8 (default) gv dd = 3.3v 89.0 42.3 ma (2)(5) 13.3 gv dd = 3.3v 55.8 26.4 ma (2)(5) 20 gv dd = 3.3v 36.6 18.1 ma (2)(5) 40 gv dd = 3.3v 18.6 9.2 ma (2)(5) drv_mem_data 20 (default) gv dd = 3.3v 36.6 18.1 ma (2)(5) 40 gv dd = 3.3v 18.6 9.2 ma (2)(5)
22 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 7.2 dynamic electri cal characteristics 7.2.1 clock ac specifications table 7-3 provides the clock ac timing specifications as defined in section. at recommended operating conditions (see table 5-2 on page 12 ) with gv dd = 3.3v 5% and lv dd = 3.3 0.3v notes: 1. these specifications are for t he default driver strengths indicated in table 7-2 on page 21 . 2. rise and fall times for the pci_sync_in input are measured from 0.4v to 2.4v. 3. specification value at maximum frequency of operation. 4. relock time is guaranteed by design and characterization. relock time is not tested. 5. rise and fall times for the osc_in input is guaranteed by de sign and characterization. osc_in input rise and fall times are not tested. 6. relock timing is guaranteed by design. pll-relock time is t he maximum amount of time required for pll lock after a stable v dd and pci_sync_in are reached during the reset sequence. th is specification also applies when the pll has been dis- abled and subsequ ently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the reset sequence. 7. dll_standard is bit 7 of the pmc2 register <72>. n is a non-zero integer (1 or 2). t clk is the period of one sdram_sync_out clock cycle in ns. t loop is the propagation delay of the dll synchronization feedback loop (pc board runner) from sdram_sync_out to sdram_sync_in in ns; 6.25 inches of loop length (unloaded pc board runner) cor- responds to approximately 1 ns of delay. see figure 7-4 on page 24 for dll locking ranges. 8. see table 8-1 on page 37 for pci_sync_in input frequency range for specific pll_cfg[0?3] settings. table 7-3. clock ac timing specifications num characteristics and conditions (1) min max unit notes 1a frequency of operation (pci_sync_in) 12.5 66 mhz (8) 1b pci_sync_in cycle time 80 15 ns (8) 2, 3 pci_sync_in rise and fall times ? 2.0 ns (2) 4 pci_sync_in duty cycle measured at 1.4v 40 60 % 5a pci_sync_in pulse width high measured at 1.4v 6 9 ns (3) 5b pci_sync_in pulse width low measured at 1.4v 6 9 ns (3) 7 pci_sync_in jitter ? < 150 ps 9a pci_clk[0?4] skew (pin to pin) ? 500 ps 9b sdram_clk[0?3] skew (pin to pin) ? 350 ps 9c cpu_clk[0?2] skew (pin to pin) ? 350 ps 9d sdram_clk[0?3]/cpu_clk[0?2] jitter ? 150 ps 10 internal pll relock time ? 100 s (3)(4)(6) 15 dll lock range with dll_standard = 1 (default) see figure 7-3 on page 23 ns (7) 16 dll lock range with dll_standard = 0 see figure 7-4 on page 24 ns (7) 17 frequency of operation (osc_in) 12.5 66 mhz (8) 18 osc_in cycle time 80 15 ns (8) 19 osc_in rise and fall times ? 5 ns (5) 20 osc_in duty cycle measured at 1.4v 40 60 % 21 osc_in frequency stability ? 100 ppm
23 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a figure 7-1 shows the pci_sync_in input clock timing diagram, figure 7-2 illustrates how table 7-3 clock specifications relate to the pc107a clocking diagram, and section 7.2.2 ?operating frequency? on page 24 shows the dll locking range loop delay vs. frequency of operation. figure 7-1. pci_sync-in input clock timing diagram figure 7-2. clock subsystem block diagram note: specification numbers are from table 7-3 . figure 7-3. dll locking range loop delay (dll_standard = 0) 1 23 5a 5b vm pci_sync_in vm vm cvih cvil vm = midpoint voltage (1.4v) dll pll core logic sys_logic_clk pci_clk[0:4] pci_sync_out pci_sync_in sdram_clk[0:3] sdram_sync_out sdram_sync_in osc_in cpu_clk[0:2] mpc107 specs. 9 c, 9 d specs. 9 b, 9 d specs. 1 - 7 spec. 9 a specs. 17 - 23 spec. 10 specs. 15,16 0 5 10 15 20 25 30 35 40 0 5 10 15 45 50 t loop propagation delay time (ns) t clk sdram_sync_out period (ns) t clk = 0.7 x t loop + 3.96 ns t clk = 0.6 x t loop + 9.27 ns t clk = 2.2 x t loop + 11.88 ns t clk = 1.8 x t loop + 27.9 ns 66 mhz 100 mhz
24 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 figure 7-4. dll locking range loop delay (dll_standard = 1) 7.2.2 operating frequency this section provides the ac electrical characteristic s for the pc107a. after fabrication, functional parts are sorted by maximum core frequency as shown in figure 7-4 and ?clock ac specifications? on page 22 and tested for conformance to the ac specifications for that frequen cy. the core frequency is deter- mined by the bus (pci_sync_in) clock freq uency and the settings of the pll_cfg[0 ? 3] signals. parts are sold by maximum processor core frequency; see ?ordering information? on page 44 . table 7-4 provides the operating frequency information for the pc107a. at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3 0.3v. note: 1. caution: the pci_sync_in frequency and pll_c fg[0?3] settings must be chosen such that the resulting peripheral logic/memory bus frequency, cpu (core) frequency, and pll (vco) frequencies do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?3] signal description in ?system design information? on page 41 for valid pll_cfg[0?3] settings and pci_sync_in frequencies. 0 5 10 15 20 25 30 35 40 0 5 10 15 45 50 table 7-4. operating frequency characteristic (1) 66 mhz 100 mhz unit min max min max core (memory bus/processor bus) frequency 25 66 25 100 mhz pci input frequency (pci_sync_in) 12.5 ? 66 mhz
25 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 7.2.3 input ac timing specifications table 7-5 provides the input ac timing specifications. see figure 7-5 on page 26 and figure 7-6 on page 26 . at recommended operating conditions (see table 5-2 on page 12 ) with gv dd = 3.3v 5% and lv dd = 3.3 0.3v notes: 1. all memory, processor and related interface input signal sp ecifications are measured from the ttl level (0.8 or 2.0v) o f the signal in question to the v m = 1.4v of the rising edge of the memory bus clock, sdram_sync_in. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 7-5 . 2. all pci signals are measured from ov dd /2 of the rising edge of pci_sync_in to 0.4*ov dd of the signal in question for 3.3 v pci signaling levels. see figure 7-6 . 3. input timings are measured at the pin. 4. t clk is the time of one sdram_sync_in clock cycle. 5. all mode select input signals specificatio ns are measured from the ttl level (0.8 or 2.0v) of the signal in question to the v m = 1.4v of the rising edge of the hreset signal. see figure 7-7 on page 26 . table 7-5. input ac timing specifications num characteristics min max unit notes 10a pci input signals valid to pci_sync_in (input setup) 3.0 ? ns (2)(3) 10b memory interface signals valid to sdram_sync_in (input setup) 2.0 ? ns (1)(3) 10c epic, misc. debug input signals valid to sdram_sync_in (input setup) 2.0 ? ns (1)(3) 10d two-wire interface input signals valid to sdram_sync_in (input setup) 2.0 ? ns (1)(3) 10e mode select inputs valid to hreset (input setup) 9*t clk ?ns (1)(3)(5) 10f 60x processor interface signals valid to sdram_sync_in (input setup) 2.0 ? ns (1)(3) 11a1 pci_sync_in (sdram_sync_in) to in puts invalid (input hold) 1.0 ? ns (2)(3) 11a2 memory interface signals sdram_sync_in to inputs invalid (input hold) 0.5 ? ns (1)(3) 11a3 60x processor interface signals sdram_sync_in to inputs invalid (input hold) 0?ns (1)(3) 11b hreset to mode select inputs invalid (input hold) 0 ? ns (1)(3)(5)
26 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 figure 7-5. input ? output timing diagram referenced to sdram_sync_in figure 7-6. input ? output timing diagram referenced to pci_sync_in figure 7-7. input timing diagram for mode select signals 11a vm vm = midpoint voltage (1.4v) memory pci_sync_in inputs/outputs 13b 14b vm vm sdram_sync_in shown in 2:1 mode input timing output timing 2.0v 0.8v 0.8v 2.0v 10b-d 12b-d ovdd/2 10a 11a pci_sync_in pci 12a 13a 14a ovdd/2 ovdd/2 0.4*ovdd 0.615*ovdd 0.285*ovdd input timing output timing inputs/outputs vm vm = midpoint voltage (1.4v) 11b mode pins 10e hreset 2.0v 0.8v
27 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 7.2.4 output ac timing specification table 7-6 provides the processor bus ac timing specifications for the pc107a. see figure 7-5 on page 26 and figure 7-6 on page 26 . at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3 0.3v notes: 1. all memory and related interface output signal specifications ar e specified from the v m = 1.4v of the rising edge of the mem- ory bus clock, sdram_sync_in to the ttl level (0.8 or 2.0v ) of the signal in question. sdram_sync_in is the same as pci_sync_in in 1:1 mode, but is twice the frequency in 2: 1 mode (processor/memory bus clock rising edges occur on every rising and falling edge of pci_sync_in). see figure 7-5 on page 26 . 2. all pci signals are measured from ov dd /2 of the rising edge of pci_sync_in to 0.285*ov dd or 0.615*ov dd of the signal in question for 3.3v pci signaling levels. see figure 7-6 on page 26 . 3. all output timings assume a purely resistive 50 ? load (see figure 7-8 on page 27 ). output timings are measured at the pin; time-of-flight delays must be added for trace lengths, vias , and connectors in the system. 4. pci bussed signals are composed of the following signals: lock , irdy , c/be [0?3], par, trdy , frame , stop , devsel , perr , serr , ad[0?31], req [4?0], gnt [4?0], idsel , inta . 5. pci hold times can be varied, see ?pci signal output hold timing? on page 28 for information on programmable pci output hold times. the values shown for item 13a are for pci compliance. 6. these specifications are for the def ault driver strengths indicated in table 7-2 on page 21 . figure 7-8. ac test load for the pc107a table 7-6. output ac timing specifications num characteristics (3)(6) min max unit notes 12a pci_sync_in to output valid, 66 mhz pci, with sdma4 pulled- down to logic 0 state. see figure 7-9 . ?6.0ns (2)(4) pci_sync_in to output valid, 33 mhz pci, with sdma4 in the default logic 1 state. see figure 7-9 . ? 11.0 ns (2)(4) 12b memory interface signals, sdram_sync_in to output valid ? 5.5 ns (1) 12b1 memory interface signal: cke (100 mhz device), sdram_sync_in to output valid ?5.5ns (1) 12b2 memory interface signal: cke (66 mhz device), sdram_sync_in to output valid ?6.0ns (1) 12c epic, misc. debug signals, sdram_sync_in to output valid ? 9.0 ns (1) 12d two-wire interface, sdram_sync_in to output valid ? 5.0 ns (1) 12e 60x processor interface signals, sdram_sync_in to output valid ? 5.5 ns (1) 13a output hold, 66 mhz pci, with sdma4 and sdma3 pulled-down to logic 0 states. see table 7-7 . 1.0 ? ns (2)(4)(5) output hold, 33 mhz pci, with sdma4 in the default logic 1 state and sdma3 pulled-down to logic 0 state. see table 7-7 . 2.0 ? ns (2)(4)(5) 13b output hold (for all others) 1 ns (1) 14a pci_sync_in to output high impedance (t off for pci) ? 14.0 ns (2)(4) 14b sdram_sync_in to output high impedance (for all others) ? 4.0 ns (1) output z0 = 50 ? ovdd/2 rl = 50 ? pin output measurements are made at the device pin.
28 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 7.2.5 pci signal output hold timing in order to meet minimum output hold specificat ions relative to pci_sync_in for both 33 mhz and 66 mhz pci systems, the pc107a has a programmabl e output hold delay for pci signals. the initial value of the output hold delay is determined by t he values on the sdma4 and sdma3 reset configura- tion signals. further output hold delay values ar e available by programming the pci_hold_del value of the pmcr2 configuration register. table 7-7 describes the bit values for the pci_hold_del values in pmcr2. table 7-7. power management configuration register 2-0x72 bit name reset value description 6 ? 4 pci_hold_del xx0 pci output hold delay values relative to pci_sync_in. the initial values of bits 6 and 5 are determined by the reset configuration pins sdma4 and sdma3 , respectively. as these two pins have internal pull-up resistors, the default value after reset is 0b110. while the minimum hold times are guaranteed at shown values, changes in the actual hold time can be made by incrementing or de crementing the value in these bit fields of this register via software or hardware confi guration. the increment is in approximately 400 picosecond steps. lowering the value in the three bit field decreases the amount of output hold available. 000 66 mhz pci. pull-down sdma4 configuration pin with a 2 k ? or less value resistor. this setting guarantees the minimum output hold, item 13a, and the maximum output valid, item 12a, times as specified in figure 7-6 are met for a 66 mhz pci system. see figure 7-9 on page 29 . 001 010 011 100 33 mhz pci. this setting guarantees the minimum output hold, item 13a, and the maximum output valid , item 12a, times as specified in figure 7-6 are met for a 33 mhz pci system. see figure 7-9 on page 29 . 101 110 (default if reset configuration pins left unconnected) 111
29 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a figure 7-9. pci_hold_del effect on output valid and hold time pci_sync_in pci inputs/outputs 33 mhz pci ovdd/2 ovdd/2 12a, 8 ns for 33 mhz pci pci_hold_del = 100 12a, 6 ns for 66 mhz pci pci_hold_del = 000 13a, 2 ns for 33 mhz pci pci_hold_del = 100 13a, 1 ns for 66 mhz pci pci_hold_del = 000 output valid output hold diagram not to scale as pci_hold_del values decrease as pci_hold_del values increase pci inputs and outputs pci inputs/outputs 66 mhz pci
30 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 7.2.6 two-wire interface ac timing specifications table 7-8 provides the two-wire interface input ac timing specifications for the pc107a. at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3 0.3v notes: 1. units for these specificati ons are in sdram_clk/cpu_clk units. 2. the actual values depend on the settin g of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register two-wire interface fdr. t herefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real time on the two-wire interface bus. the qualified scl, sda signals are delayed by the sdram_clk/cpu_clk clock times dffsr times 2 plus 1 sdram_clk/cpu_clk clock. the resulting delay value is added to the val ue in the table (where this note is referenced). see figure 7-11 on page 33 . 3. timing is relative to the sampling clock (not scl). 4. fdr[x] refers to the frequency divider register i2cfdr bit x. 5. input clock low and high periods in combination with the f dr value in the frequency divider register (i2cfdr) determine the maximum two-wire interface input frequency. see figure 7-11 on page 33 . table 7-8. two-wire interface input ac timing specifications num characteristics min max unit notes 1 start condition hold time 4.0 ? clks (1)(2) 2 clock low period (the time before the pc107a will drive scl low as a transmitting slave after detecting scl low as driven by an external master) 8.0 + (16 2 fdr[4:2] ) (5 - 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ?clks (1)(2)(4)(5) 3 scl/sda rise time (from 0.5v to 2.4v) ? 1 ms 4 data hold time 0 ? ns (2) 5 scl/sda fall time (from 2.4v to 0.5v) ? 1 ms 6 clock high period (time needed to either receive a data bit or generate a start or stop) 5.0 ? clks (1)(2)(5) 7 data setup time 3.0 ? ns (3) 8 start condition setup time (for repeated start condition only) 4.0 ? clks (1)(2) 9 stop condition setup time 4.0 ? clks (1)(2)
31 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a table 7-9 provides the two-wire interface frequency divider register (i2cfdr) information for the pc107a. at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3v 5% notes: 1. values are in khz unless otherwise specified. 2. fdr hex and divider (dec) values are listed in corresponding order. 3. multiple divider (dec) values will generate the same input fr equency but each divider (dec) value will generate a unique out- put frequency as shown in table 7-10 on page 32 . table 7-9. pc8240 maximum two-wire interface input frequency fdr hex (2) divider (dec) (2) max two-wire interfa ce input frequency (1) sdram_clk/ cpu_clk at 25 mhz sdram_clk/ cpu_clk at 33 mhz sdram_clk/ cpu_clk at 50 mhz sdram_clk/ cpu_clk at 100 mhz 20, 21 160, 192 862 1.13 mhz 1.72 mhz 3.44 mhz 22, 23, 24, 25 224, 256, 320, 384 555 733 1.11 mhz 2.22 mhz 0, 1 288, 320 409 540 819 1.63 mhz 2, 3, 26, 27, 28, 29 384, 448, 480, 512, 640, 768 324 428 649 1.29 mhz 4, 5 576, 640 229 302 458 917 6, 7, 2a, 2b, 2c, 2d 768, 896, 960, 1024, 1280, 1536 177 234 354 709 8, 9 1152, 1280 121 160 243 487 a, b, 2e, 2f, 30, 31 1536, 1792, 1920, 2048, 2560, 3072 92 122 185 371 c, d 2304, 2560 62 83 125 251 e, f, 32, 33, 34, 35 3072, 3584, 3840, 4096, 5120, 6144 47 62 95 190 10, 11 4608, 5120 32 42 64 128 12, 13, 36, 37, 38, 39 6144, 7168, 7680, 8192, 10240, 12288 24 31 48 96 14, 15 9216, 10240 16 21 32 64 16, 17, 3a, 3b, 3c, 3d 12288, 14336, 15360, 16384, 20480, 24576 12 16 24 48 18, 19 18432, 20480 8 10 16 32 1a, 1b, 3e, 3f 24576, 28672, 30720, 32768 681224 1c, 1d 36864, 40960 4 5 8 16 1e, 1f 49152, 61440 3 4 6 12
32 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 table 7-10 provides the two-wire interface output ac timing specifications for the pc107a. at recommended operating conditions (see table 5-2 on page 12 ) with gv dd = 3.3v 5% and lv dd = 3.3 0.3v notes: 1. units for these specificati ons are in sdram_clk/cpu_clk units. 2. the actual values depend on the settin g of the digital filter frequency sampling rate (dffsr) bits in the frequency divider register i2cfdr. therefore, the noted timings in the above table are all relative to qualified signals. the qualified scl and sda are delayed signals from what is seen in real ti me on the two-wire interface bus. the qualified scl, sda sig- nals are delayed by the sdram_clk/cpu_clk clock times dffsr times 2 plus 1 sdram_clk/cpu_clk clock. the resulting delay value is added to the value in t he table (where this note is referenced). see figure 7-11 on page 33 . 3. since scl and sda are open-drain type outputs, which the pc107a can only drive low, the time required for scl or sda to reach a high level depends on external signal capacitance and pull-up resistor values. 4. specified at a nominal 50 pf load. 5. d fdr is the decimal divider number indexed by fdr[5:0] value. refer to the two-wire interface chapter?s serial bit clock fre- quency divider selections table. fdr[x] refers to the frequen cy divider register i2cfdr bit x. n is equal to a variable number that would make the result of the divide (data hold time value) equal to a number less than 16. m is equal to a vari- able number that would make the result of the divide (data hold time value) equal to a number less than 9. figure 7-10. two-wire interface timing diagram ii table 7-10. two-wire interface output ac timing specifications num characteristics min max unit notes 1 start condition hold time (fdr[5] == 0) (d fdr /16) / 2n + (fdr[5] == 1) (d fdr /16) / 2m ?clks (1)(2)(5) 2 clock low period d fdr / 2 ? clks (1)(2)(5) 3 scl/sda rise time (from 0.5v to 2.4v) ? ? ms (3) 4 data hold time 8.0 + (16 2 fdr[4:2] ) (5 - 4({fdr[5],fdr[1]} == b?10) - 3({fdr[5],fdr[1]} == b?11) - 2({fdr[5],fdr[1]} == b?00) - 1({fdr[5],fdr[1]} == b?01)) ?clks (1)(2)(5) 5 scl/sda fall time (from 2.4v to 0.5v) ? < 5 ns (4) 6 clock high time d fdr / 2 ? clks (1)(2)(5) 7 data setup time (pc107a as a master only) (d fdr / 2) - (output data hold time) ? clks (1)(5) 8 start condition setup time (for repeated start condition only) d fdr + (output start condition hold time) ?clks (1)(2)(5) 9 stop condition setup time 4.0 ? clks (1)(2) scl sda vm vm 6 2 1 4
33 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a figure 7-11. two-wire interface timing diagram ii figure 7-12. two-wire interface timing diagram iii note: dffsr filter clock is the sdram_clk clock times dffsr value. figure 7-13. two-wire interface timing diagram iv (qualified signal) note: the delay is the local memory clock ti mes dffsr times 2 plus 1 local memory clock. scl sda vm vl vh 9 8 3 5 input data valid dffsr filter clk (1) sda 7 scl/sdarealtime vm scl/sdaqualified vm delay (1)
34 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 7.2.7 epic serial interrupt mode ac timing specifications table 7-11 provides the epic serial interrupt mode ac timing specifications for the pc107a. at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3 0.3v notes: 1. see the pc107a user?s manual for a description of the epic interrupt control register (e icr) describing s_clk frequency programming. 2. s_rst, s_frame , and s_int shown in figure 7-14 and figure 7-15 depict timing relation ships to sys_logic_clk and s_clk and do not describe functional relationships between s_rst, s_frame , and s_int. see the pc107a user?s man- ual for a complete description of the functional relationships between these signals. 3. the sys_logic_clk waveform is the clocking signal of the intern al peripheral logic from the output of the peripheral logic pl l; sys_logic_clk is the same as sdram_sync_in when the sdram_sync_out to sdram_sync_in feedback loop is implemented and the dll is locked. see the pc107a user?s manual for a complete clocking description. figure 7-14. epic serial interrupt mode output timing diagram figure 7-15. epic serial interrupt mode input timing diagram table 7-11. epic serial interrupt mode ac timing specifications num characteristics min max unit notes 1 s_clk frequency 1/14 sdram_sync_in 1/2 sdram_sync_in mhz (1) 2 s_clk duty cycle 40 60 % 3 s_clk output valid time ? 6 ns 4 output hold time 0 ? ns 5s_frame , s_rst output valid time ? 1 sys_logic_clk period + 6 ns (2) 6 s_int input setup time to s_ clk 1 sys_logic_clk period + 2 ? ns (2) 7 s_int inputs invalid (h old time) to s_clk ? 0 ns (2) s_clk s_rst vm vm vm s_frame sys_logic_clk3 vm vm vm vm 4 3 5 4 s_clk s_int vm 6 7
35 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 7.2.8 ieee 1149.1 (jtag) ac timing specifications table 7-12 provides the jtag ac timing specifications for the pc107a while in the jtag operating mode. at recommended operating conditions (see table 5-2 on page 12 ) with lv dd = 3.3 0.3v notes: 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test (other than tdi and tms) si gnal input timing with respect to tck. 3. non-test (other than tdo) signal output timing with respect to tck. 4. timings are independent of the system clock (pci_sync_in). figure 7-16. jtag clock input timing diagram table 7-12. jtag ac timing specifications (independent of pci_sync_in) num characteristics (4) min max unit notes tck frequency of operation 0 25 mhz 1 tck cycle time 40 ? ns 2 tck clock pulse width measured at 1.5v 20 ? ns 3 tck rise and fall times 0 3 ns 4 trst_ setup time to tck falling edge 10 ? ns (1) 5 trst_ assert time 10 ? ns 6 boundary scan input data setup time 5 ? ns (2) 7 boundary scan input data hold time 15 ? ns (2) 8 tck to output data valid 0 30 ns (3) 9 tck to output high impedance 0 30 ns (3) 10 tms, tdi data setup time 5 ? ns 11 tms, tdi data hold time 15 ? ns 12 tck to tdo data valid 0 15 ns 13 tck to tdo high impedance 0 15 ns tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage
36 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 figure 7-17. jtag trst timing diagram figure 7-18. jtag boundary scan timing diagram figure 7-19. test access port timing diagram 4 5 trst tck 6 7 input data valid 8 9 output data valid tck data inputs data outputs data outputs input data valid output data valid 10 11 12 13 tck tdi, tms tdo tdo
37 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 8. preparation for delivery 8.1 packaging microcircuits are prepared for delivery in accordance with internal standards. 8.2 certificate of compliance e2v offers a certificate of compliance with each ship ment of parts, affirming the products are in compli- ance either with internal specifications and guaranteeing the parameters not tested at temperature extremes for the entire temperature range. 8.3 handling mos devices must be handled with certain precautions to avoid damage due to accumulation of static charge. input protection devices have been designed in the chip to minimize the effect of this static buildup. however, the following handling practices are recommended: devices should be handled on benche s with conductive and grounded surfaces ground test equipment, tools and operator do not handle devices by the leads store devices in conductive foam or carriers avoid use of plastic, rubber or silk in mos areas maintain relative humidity above 50% if practical 8.4 choice of cl ock relationships the pc107a?s internal pll is configured by the pll_cfg[0 ? 3] signals. for a given pci_sync_in (pci bus) frequency, the pll configuration signals set the core/memory/processor pll (vco) frequency of operation for the pci-to-core/memory/processor frequ ency multiplying, if any. all valid pll configura- tions for the pc107a are shown in table 8-1 . table 8-1. pc107a microprocessor pll configuration ref pll_cfg [0 ? 3] (2) 66 mhz part 100 mhz part pci: core ratio vco multiplier pci_sync_in range (mhz) core/mem/cpu range (mhz) pci_sync_in range (mhz) core/mem/cpu range (mhz) 1 0001 25 (5) ? 33 25 ? 33 25 (5) ? 50 (4) 25 ? 50 1 4 2 0010 13 (5) ? 16 (4) 26 ? 34 13 (5) ? 25 (4) 26 ? 50 2 4 3 0011 bypass bypass bypass bypass 5 0101 25 (5) ? 33 50 ? 66 25 (5) ? 50 50 ? 100 2 2 8 1000 17 (5) ? 22 51 ? 66 17 (5) ? 33 50 ? 100 3 2 9 1001 34 (5) ? 44 51 ? 66 33 (5) ? 66 50 ? 100 1.5 2 a 1010 13 (4) ? 16 (7) 52?64 13 (4) ? 25 (7) 52?100 4 2 c 1100 20 (5) ? 26 50 ? 65 20 (5) ? 40 50 ? 100 2.5 2 d 1101 50 (5) ? 66 50 ? 66 50 (5) ? 66 50 ? 66 1 2 f 1111 clock off (3) not usable clock off (3) not usable off off
38 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 notes: 1. pll_cfg[0?3] settings not listed (00000100, 0110, 0111, 1010, 1011, and 1110) are reserved. 2. in pll bypass mode, the pci_sync_in input signal clocks the inte rnal core directly, the pll is disabled, and the pci: core mode is set for 1:1 mode operation. the ac timing specifications given in this document do not apply in pll bypass mode. 3. in clock off mode, no clocking occurs inside the pc107a regardless of the pci_sync_in input. 4. limited due to maximum memory vco = 200 mhz. 5. limited due to minimum vco = 100 mhz. 6. range values are shown rounded down to the nearest whol e number (decimal place accuracy removed) for clarity. 7. limited by maximum memory bus speed. 9. package mechanical data 9.1 package parameters the pc107a uses a 33 mm 33 mm, 503 pin plastic ball grid arra y (pbga) or hitce "ceramic ball grid array (cbga)" package. the plastic package parameters are as provided in the following list. table 9-1. package parameters parameter hitce-cbga fc-pbga package outline 33 mm 33 mm 33 mm 33 mm interconnects 503 503 pitch 1.27 mm 1.27 mm solder attach 10 sn/9 0 pb 62 sn/36 pb/2 ag solder balls 10 sn/90 pb 62 sn/36 pb/2 ag solder balls diameter 0.60 mm ? 0.90 mm 0.60 mm ? 0.90 mm maximum module height 3.20 2.75 mm co-planarity specification 0.20 mm 0.20 mm maximum force 6.0 lbs. total, uniformly distributed over package (5.4 grams/ball) 6.0 pbs. total, uniformly distributed over package (5.4 grams/ball)
39 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 9.2 mechanical dimensions figure 9-1 shows the top surface, side profile, and pinout of the pc107a, 503 pbga package. figure 9-1. pc107a package dimensions and pinout assignments notes: 1. dimensioning and tolerancing per a. 2. dimensions in mill imeters. 3. dimension b is the maximum solder ball diame ter meas ured parallel to datum a. 4. d2 and e2 define the are a occupied on the die and underfill actual size of this area may be smaller than shown. d3 and e3 are the mini mum clearance from the package edg e to the chip capacitors. 5. capacitors may not be present on all devices. 6. caution must be taken not to short expos e metal capacitor pads on packag e top. 0.3 0.15 c b a a millimeters dim min max a 2.75 a1 0.50 0.70 a2 1.00 1.20 a3 0.80 a4 0.82 0.90 b 0.60 0.90 c 33 bsc d1 30.48 bsc d2 12.50 d3 3.43 d4 5.00 e 1.27 bsc e 33 bsc e1 30.48 bsc e2 14.50 e3 3.43 e4 9.00 0.2 4x 33 12.5 max 5 min 33 14.5 max top view 9 min b a1 index 4 c 4 a 0.2 a 0.25 a // side view 0.35 a // 0.9 0.82 1.2 1 2.75 max 0.7 0.5 503x seating plane 24xe d1 13 5 7 9 1113151719212325 2 6 10 12 14 16 18 20 22 24 ae a b ad ac ab aa c d e f g h j k l m n p r t u v w c 503 x ? b e1 24xe 48 bottom view y
40 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 figure 9-2. mechanical dimensions and bottom surface nomenclature of the 503-ball hitce cbga package c a b 0.3 b (503x) bottom view e1 e (24x) e (24x) d1 13 2 5 4 7 6 9 8 11 10 13 12 15 14 17 16 19 18 21 20 23 25 22 24 ae ad ab y v t p m k h f d b ac aa w u r n l j g e c a 0.2 2x -a- d5 (2x) d3 (2x) chamfer: c (4x) top view e3 (2x) 0.2 2x -b- e e2 e4 e5 (2x) d d2 d4 ball index a1 1 107 0.2 -c- a4 a2 a1 a side view all dimension in mm a a1 a2 a3 a4 b d d1 d2 d3 d4 e e e1 e2 e3 e4 2.72 0.80 1.08 ? 0.82 0.82 32.80 3.72 5.50 1.27 basic 32.80 3.72 8.90 3.20 1.00 1.32 ? 0.90 0.93 33.20 11.0 3.92 5.70 33.20 14.4 3.92 9.10 parameter min max 30.48 basic (1.27 x 24) 30.48 basic (1.27 x 24)
41 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 10. system design information 10.1 pll power supply filtering the av dd and lav dd power signals are provided on the pc107a to provide power to the peripheral logic/memory bus pll and the sdram clock delay-loc ked loop (dll), respectively. to ensure stability of the internal clocks, the power supplied to the av dd and lav dd input signals should be filtered of any noise in the 500 khz to 10 mhz resonant frequency range of the plls. a separate circuit similar to the one shown in figure 10-1 using surface mount capacitors with minimum effective series inductance (esl) is recommended for each of the av dd and lav dd power signal pins. consistent with the recom- mendations of dr. howard johnson in high speed digital design: a handbook of black magic (prentice hall, 1993), multiple small capacitors of equal value are recommended over using multiple values. the circuits should be placed as clos e as possible to the respective i nput signal pins to minimize noise coupled from nearby circuits. routing directly as possib le from the capacitors to the input signal pins with minimal inductance of vias is important but proportionately less critical for the lav dd pin. figure 10-1. pll power supply filter circuit 10.2 power supply voltage sequencing the notes in table 5-2 on page 12 contain cautions illustrated in figure 5-1 on page 13 about the sequencing of the external bus voltages and internal voltages of the pc107a. these cautions are neces- sary for the long term reliability of the part. if they are violated, the electrostatic discharge (esd) protection diodes will be forward biased and exce ssive current can flow through these diodes. figure 5-1 shows a typical ramping voltage sequence where the dc power sources (voltage regulators and/or power supplies) are connected as shown in figure 10-2 . the voltage regulator delay shown in figure 5- 1 can be zero if the various dc voltage levels are all applied to the target board at the same time. the ramping voltage sequence shows a scenario in which the v dd /av dd /lav dd power plane is not loaded as much as the ov dd /gv dd power plane and thus v dd /av dd /lav dd ramps at a faster rate than ov dd /gv dd . if the system power supply design does not control the voltage sequencing, the circuit of figure 10-2 can be added to meet these requirements. the mur420 diodes of figure 10-2 control the maximum poten- tial difference between the 3.3 bus and internal voltages on power-up and the 1n5820 schottky diodes regulate the maximum potential difference on power-down. figure 10-2. example voltage sequencing circuits vdd avdd or lavdd 10 ? 2.2 f 2.2 f gnd low esl surface mount capacitors + 5v source + 3.3v source 5v 3.3v 3.3v mur420 mur420 in5820 in5820 2.5v 2.5v + 2.5v source
42 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 10.3 decoupling recommendations due to the pc107a?s dynamic power management feature, large address and data buses, and high operating frequencies, the pc107a can generate transi ent power surges and high frequency noise in its power supply, especially wh ile driving large capacitive loads. th is noise must be prevented from reach- ing other components in the pc107a system, and the pc107a itself requ ires a clean, tightly regulated source of power. therefore, it is recommended t hat the system designer place at least one decoupling capacitor at each v dd , ov dd , gv dd , and lv dd pin of the pc107a. it is also recommended that these decoupling capacitors receive their power from separate v dd , ov dd , gv dd , and gnd power planes in the pcb, utilizing short traces to minimi ze inductance. these capacitors sh ould have a value of 0.1 f. only ceramic smt (surface mount technol ogy) capacitors should be used to minimize lead inductance, pref- erably 0508 or 0603, oriented such that connections are made along the length of the part. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the v dd , ov dd , gv dd , bv dd , and lv dd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they shoul d also be connected to the power and ground planes through two vias to minimize induct ance. suggested bulk capacitors-100 ? 330 f (avx tps tantalum or sanyo oscon). 10.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to ov dd . unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external v dd , ov dd , gv dd , lv dd , bv dd , and gnd pins of the pc107a. the pci_sync_out signal is intended to be routed halfway out to the pci devices and then returned to the pci_sync_in input of the pc107a. the sdram_sync_out signal is intended to be routed halfway out to the sdram devices and then returned to the sdram_sync_in input of the pc107a. the trace length may be used to skew or adjust the timing window as needed. see freescale ? application note "an1794/d" for more information on this topic. the trst signal must be asserted during reset to ensure proper initialization and operation of the pc107a. it is recommended that the trst signal be connected to the system hreset signal or pulled down with a 100 ? - 1 k ? resistor.
43 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a 10.5 pull-up/pull-down resistor requirements the data bus input receivers are normally turned off when no read operation is in progress; therefore, they do not require pull-up resistors on the bus. the processor data bus signals are: dh[0 ? 31], dl[0 ? 31], and par[0 ? 7]. the memory data bus signals are: mdh[0 ? 31], mdl[0 ? 31], and par/ar[0 ? 7]. if the 32-bit data bus mode is selected, the input receivers of the unused data and parity bits (dl[0 ? 31], dp[4 ? 7], mdl[0 ? 31], and par[4 ? 7]) will be disabled, and their outputs will drive logic zeros when they would otherwise normally be driven. for this mode, these pins do not require pull-up resistors, and should be left unconnected by the system to minimize possible output switching. it is recommended that artry , ta , and ts have weak pull-up resistors (2 k ? ? 10 k ? ) connected to bv dd . it is recommended that mtp[1 ? 2] and test2 have weak pull-up resistor (2 k ? ? 10 k ? ) connected to gv dd . it is recommended that the following signals be pulled up to ov dd with weak pull-up resistors (2 k ? ? 10 k ? ): sda, scl, test1 , and ftp[3 ? 3]. it is recommended that the following pci control signals be pulled up to lv dd with weak pull-up resistors (2 k ? ? 10 k ? ): devsel , frame , irdy , lock , perr , serr , stop , trdy and inta . the resistor val- ues may need to be adjusted stronger to reduce induced noise on specific board designs. the following pins have internal pull- up resistors enabled at all times: req [06 ? 4], tck, tdi, tms, and trst , br1 , hreset_cpu , mcp , qack , sreset , test and trig_out . see table 2-1, ?pc107a pinout listing,? on page 5 for more information. the following pins have internal pull-up resistors enabl ed only while device is in the reset state: mdl0, foe , rcs0 , sdras , sdcas , cke, sdbao, and sdma[10 ? 1]. see table 2-1, ?pc107a pinout list- ing,? on page 5 for more information. the following pins are reset configuration pins: mdl0, foe , rcs0 , sdbao, sdma[10 ? 1], and pll_cfg[0 ? 3]. these pins are sampled during reset to configure the device. any other unused active low input pins should be tied to a logic one level via weak pull-up resistors (2 k ? ? 10 k ? ) to the appropriate power supply listed in table 5-2 on page 12 . unused active high input pins should be tied to gnd via weak pull-down resistors (2 k ? ? 10 k ? ).
44 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 11. definitions 11.1 life support applications these products are not designed for use in life s upport appliances, devices or systems where malfunc- tion of these products can reasonably be expected to result in personal injury. e2v customers using or selling these products fo r use in such applications do so at thei r own risk and agree to fully indemnify e2v for any damages resulting from such improper use or sale. 12. ordering information notes: 1. for availability of the different versions, contact your local e2v sales office. 2. the letter x in the part number designates a "prototype" pr oduct that has not been qualified by e2v. reliability of a pcx par t- number is not guaranteed and such part-number shall not be us ed in flight hardware. product changes may still occur while shipping prototypes. 13. document revision history table 13-1 provides a revision history for this hardware specification. l: 2.5 125 mv c = 1.3 d = 1.4 part identifier 107a product code (1) pc(x) (2) package (1) revision level (1) temperature range: t j (1) screening level operating frequency bus divider m: -55?c, +125?c v: -40?c, +110?c zf: fc-pbga (2) u: upscreening test blank: standard 100: 100 mhz gh: hitce - cbga table 13-1. document revision history revision number date substantive change(s) e 04/2007 name from atmel to e2v ordering information update d 09/2004 final specification afte r qualification product motorola changed to freescale c 06/2006 add hitce package with thermal characteristics (see table 6-2 on page 16 ) ordering information ( see ?ordering information? on page 44. )
i 0842e?hirel?04/07 e2v semiconductors sas 2007 pc107a table of contents features ................. .............. .............. .............. .............. .............. ............. 1 description ......... ................. .............. .............. .............. .............. ............. 1 screening ........... ................. .............. .............. .............. .............. ............. 2 1 general description .. ................. ................ ................. ................ ............. 2 1.1 simplified block diagram ....................................................................................... 2 1.2 features ................................................................................................................. 3 2 pin assignments .......... ................ ................ ................. .............. ............. 5 2.1 pinout listings ........................................................................................................ 5 3 signal description .............. .............. .............. .............. .............. ........... 10 4 detailed specification ........ .............. .............. .............. .............. ........... 11 5 applicable documents ........... ................. ................ ................. ............. 11 5.1 design and construction ...................................................................................... 11 5.2 absolute maximum ratings .................................................................................. 11 5.3 recommended operating conditions .................................................................. 12 6 thermal information ........... .............. .............. .............. .............. ........... 15 6.1 package characteristics ....................................................................................... 15 6.2 power characteristics .......................................................................................... 19 7 electrical characteristics ... .............. .............. .............. .............. ........... 20 7.1 static characteristics ............................................................................................ 20 7.2 dynamic electrical characteristics ....................................................................... 22 8 preparation for delivery ....... .............. .............. .............. .............. ......... 37 8.1 packaging ............................................................................................................. 37 8.2 certificate of compliance ..................................................................................... 37 8.3 handling ............................................................................................................... 37 8.4 choice of clock relationships .............................................................................. 37 9 package mechanical data ...... ................. ................ ................. ............. 38 9.1 package parameters ............................................................................................ 38 9.2 mechanical dimensions ....................................................................................... 39 10 system design information ... ................. ................ ................. ............. 41 10.1 pll power supply filtering .................................................................................. 41
ii 0842e?hirel?04/07 pc107a e2v semiconductors sas 2007 10.2 power supply voltage sequencing ..................................................................... 41 10.3 decoupling recommendations ........................................................................... 42 10.4 connection recommendations ........................................................................... 42 10.5 pull-up/pull-down resistor requirements ........................................................... 43 11 definitions ............. .............. .............. .............. .............. .............. ........... 44 11.1 life support applications ..................................................................................... 44 12 ordering information ............ .............. .............. .............. .............. ......... 44 13 document revision history .. ............. .............. .............. .............. ......... 44 table of contents ................. .............. .............. .............. .............. ............ i
whilst e2v has taken care to ensure the accuracy of the info rmation contained herein it accept s no responsibility for the conse quences of any use thereof and also reserves the right to change the specific ation of goods without notice. e2v accepts no liability beyond th at set out in its stan- dard conditions of sale in respect of infringement of third party patents arising from the use of tubes or other devices in acc ordance with informa- tion contained herein. how to reach us home page: www.e2v.com sales office: northern europe e2v ltd 106 waterhouse lane chelmsford essex cm1 2qu england tel: +44 (0)1245 493493 fax: +44 (0)1245 492492 e-mail: enquiries@e2v.com southern europe e2v sas 16 burospace f-91572 bivres cedex france tel: +33 (0) 16019 5500 fax: +33 (0) 16019 5529 e-mail: enquiries-fr@e2v.com germany and austria e2v gmbh industriestra?e 29 82194 gr?benzell germany tel: +49 (0) 8142 41057-0 fax: +49 (0) 8142 284547 e-mail: enquiries-de@e2v.com americas e2v inc. 4 westchester plaza elmsford ny 10523-1482 usa tel: +1 (914) 592 6050 or 1-800-342-5338, fax: +1 (914) 592-5148 e-mail: enquiries-na@e2v.com asia pacific e2v bank of china tower 30th floor office 7 1 garden rd central hong kong tel: +852 2251 8227/8/9 fax: +852 2251 8238 e-mail: enquiries-hk@e2v.com product contact: e2v avenue de rochepleine bp 123 - 38521 saint-egrve cedex france tel: +33 (0)4 76 58 30 00 hotline : std-hotline@e2v.com 0842e?hirel?04/07 e2v semiconductors sas 2007

▲Up To Search▲

Price & Availability of PCX107AMZFU100LC

	To Download PCX107AMZFU100LC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .